Abstract
High-speed embedded systems are increasingly critical in applications ranging from autonomous vehicles to real-time signal processing. To meet stringent performance, power, and area constraints, Very Large Scale Integration (VLSI) design methodologies have evolved toward high-throughput, low-latency, and energy-efficient architectures. This paper explores advanced VLSI techniques including pipelined datapaths, clock domain optimization, asynchronous design strategies, and hardware-software co-design. The study also evaluates key trade-offs in ASIC versus FPGA deployment and presents a comparative performance analysis. The proposed approaches highlight the need for co-optimization across architecture, logic, and physical design domains in embedded applications.
All articles published in the American Journal of Embedded Systems and VLSI Design (AJESVD) are licensed under the Creative Commons Attribution 4.0 International License (CC BY 4.0). This license allows:
-
Sharing – copying and redistributing the material in any medium or format
-
Adaptation – remixing, transforming, and building upon the material for any purpose, even commercially
Under the following terms:
-
Attribution – You must give appropriate credit, provide a link to the license, and indicate if changes were made. You may do so in any reasonable manner but not in any way that suggests the licensor endorses you or your use.
By submitting a manuscript to AJESVD, authors agree to make their work freely available under the terms of the CC BY 4.0 license and affirm that their submission is original and does not infringe on any third-party rights.