Balancing Thermal and Timing Objectives in Physical Synthesis through Pareto Policy Optimization

Abstract

Modern integrated circuit design faces escalating challenges in simultaneously optimizing thermal characteristics and timing performance during physical synthesis. As semiconductor technology nodes continue to shrink, interconnect delays dominate circuit behavior while power density constraints impose strict thermal management requirements. This paper presents a comprehensive investigation into applying Pareto policy optimization frameworks for achieving balanced thermal-timing objectives in physical synthesis workflows. We examine the fundamental trade-offs between minimizing peak temperatures and meeting stringent timing constraints, exploring how multi-objective optimization strategies can navigate this complex design space. Our analysis reviews current methodologies in thermal-aware placement, timing-driven optimization techniques, and demonstrates how Pareto-based approaches enable designers to explore optimal trade-off frontiers systematically. The proposed framework integrates thermal modeling with static timing analysis (STA) during incremental physical synthesis stages, allowing simultaneous consideration of temperature-dependent delays and power dissipation patterns. Results from our comprehensive literature analysis indicate that Pareto optimization provides superior flexibility compared to traditional weighted-sum methods, enabling exploration of non-convex solution spaces while preserving solution diversity. This work contributes to advancing design automation methodologies for next-generation high-performance computing systems where thermal and timing closure represent co-equal first-order constraints.